let x, y, z be set ; :: thesis: ( x in the carrier of (BitGFA1Str (x,y,z)) & y in the carrier of (BitGFA1Str (x,y,z)) & z in the carrier of (BitGFA1Str (x,y,z)) & [<*x,y*>,xor2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*[<*x,y*>,xor2c],z*>,xor2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*x,y*>,and2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*y,z*>,and2a] in the carrier of (BitGFA1Str (x,y,z)) & [<*z,x*>,and2] in the carrier of (BitGFA1Str (x,y,z)) & [<*[<*x,y*>,and2c],[<*y,z*>,and2a],[<*z,x*>,and2]*>,or3] in the carrier of (BitGFA1Str (x,y,z)) )
set f1 = and2c ;
set f2 = and2a ;
set f3 = and2 ;
set f4 = or3 ;
set f0 = xor2c ;
set xy = [<*x,y*>,and2c];
set yz = [<*y,z*>,and2a];
set zx = [<*z,x*>,and2];
set xyz = [<*[<*x,y*>,and2c],[<*y,z*>,and2a],[<*z,x*>,and2]*>,or3];
set S1 = GFA1AdderStr (x,y,z);
set S2 = GFA1CarryStr (x,y,z);
A1: ( x in the carrier of (GFA1AdderStr (x,y,z)) & y in the carrier of (GFA1AdderStr (x,y,z)) ) by FACIRC_1:60;
A2: ( z in the carrier of (GFA1AdderStr (x,y,z)) & [<*x,y*>,xor2c] in the carrier of (GFA1AdderStr (x,y,z)) ) by FACIRC_1:60, FACIRC_1:61;
A3: [<*[<*x,y*>,and2c],[<*y,z*>,and2a],[<*z,x*>,and2]*>,or3] in the carrier of (GFA1CarryStr (x,y,z)) by Th47;
A4: ( [<*y,z*>,and2a] in the carrier of (GFA1CarryStr (x,y,z)) & [<*z,x*>,and2] in the carrier of (GFA1CarryStr (x,y,z)) ) by Th47;
( [<*[<*x,y*>,xor2c],z*>,xor2c] in the carrier of (GFA1AdderStr (x,y,z)) & [<*x,y*>,and2c] in the carrier of (GFA1CarryStr (x,y,z)) ) by Th47, FACIRC_1:61;
hence ( x in the carrier of (BitGFA1Str (x,y,z)) & y in the carrier of (BitGFA1Str (x,y,z)) & z in the carrier of (BitGFA1Str (x,y,z)) & [<*x,y*>,xor2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*[<*x,y*>,xor2c],z*>,xor2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*x,y*>,and2c] in the carrier of (BitGFA1Str (x,y,z)) & [<*y,z*>,and2a] in the carrier of (BitGFA1Str (x,y,z)) & [<*z,x*>,and2] in the carrier of (BitGFA1Str (x,y,z)) & [<*[<*x,y*>,and2c],[<*y,z*>,and2a],[<*z,x*>,and2]*>,or3] in the carrier of (BitGFA1Str (x,y,z)) ) by A1, A2, A4, A3, FACIRC_1:20; :: thesis: verum